In a semiconductor device manufacturing process, an etching target layer is etched with a mask in order to form a desired shape, e.g., a groove or a hole, in the etching target layer. As for the mask for use in etching the etching target layer, a resist mask may be used. Alternatively, a hard mask may be formed by etching a layer having selectivity to the etching target layer with the resist mask.
In order to etch the etching target layer or a layer to be used as the mask later, the resist mask for use in etching is exposed to an etchant gas and a plasma thereof. Therefore, the resist mask needs to have etching resistance to the etchant gas and the plasma thereof.
A curing (hardening) process using a plasma of hydrogen gas has been conventionally used as a processing method for increasing the etching resistance of the resist mask. Such a processing method is disclosed in Non-Patent Document 1. In the method disclosed in Non-Patent Document 1, the resist mask is cured by the plasma of the hydrogen gas supplied to an inductively coupled plasma processing apparatus.
Non-Patent Document 1: Myeong-Cheol Kim et al., “Effects of various plasma Pretreatments on 193 nm photoresist and linewidth roughness after etching”, JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 24 (6), November/December 2006, pages 2645 to 2652
According to Non-Patent Document 1, when the resist mask is first processed by using the plasma of the hydrogen gas and then a hard mask is formed by etching using the processed resist mask, the resist mask having 70 nm line feature has a variation in the linewidth, i.e., linewidth roughness (LWR), of about 9 nm.
Generally, the variation in the linewidth of the resist mask is reflected in the hard mask. Therefore, when the etching target layer is etched by using the hard mask, the variation in the linewidth of the resist mask is reflected in the shape formed in the etching target layer. This may further deteriorate characteristics of a semiconductor device including the etching target layer.
For example, in a MOS transistor having a gate formed by using the hard mask, which is formed by the method disclosed in Non-Patent Document 1, a channel length designed to be 70 nm may be changed to 79 nm. Here, a current Ids between a source and a drain of the MOS transistor satisfies relationship of the following Eq. (1):
                              I          ds                =                              μ            eff                    ⁢                      C            ox                    ⁢                      W            L                    ⁢                      (                                          V                g                            -                              V                t                                      )                    ⁢                      V            ds                                              Eq        .                                  ⁢                  (          1          )                    
where μeff indicates the effective channel mobility; Cox indicates the gate oxide capacitance per unit area; W indicates the channel width; L indicates the channel length; Vg indicates the gate voltage; Vt indicates the threshold voltage; and Vds indicates the voltage between the source and the drain.
As can be seen from Eq. (1), the current Ids between the source and the drain is in inverse proportion to the channel length L. Therefore, when the channel length, which is designed to be 70 nm, becomes 79 nm, the current Ids is decreased by about 12% compared to the case of the channel length of 70 nm. During the operation of the MOS transistor, ON current Ion needs to be maintained at a constant level. Therefore, in order to deal with the decrease of the current Ids, a power supply voltage needs to be increased. For example, the power supply voltage needs to be increased by about 13% to make the current Ids in the case of the channel length of 79 nm identical to the current Ids in the case of the channel length of 70 nm. As a consequence, the power consumption is increased. Further, the variation in the channel length may deteriorate ON current/OFF current characteristics of the MOS transistor.